The present invention relates to a rounding operation circuit used in an image signal processor.
According to the amendment of the recommendation H.261 of the CCITT p.times.64 bits/sec. television phone coding system, chances are that a system for DCT (discrete cosine transform) coding between motion compensating frames will be adopted. In this recommendation, an allowable range of the inverted DCT operating error is defined in order to suppress the mismatch of the coded image attended with transmission and reception. These are based on the content of "CCITT SGXV WP XV/1 Specialist Group on Coding for Visual Telephony, Doc, #584, (1988-11)".
In the reverse DCT operation, there is included a so-called rounding operation which cuts off the most significant 16 bits after 1 is added to, for example, the fifteenth bit of 31 bits as counted from below. As this rounding method, various means are conceivable, but it is reported that the foregoing reverse DCT operating error becomes minimal by carrying out the rounding operation symmetrically relative to the positive and negative (that is, rounding to the hearest whole number for absolute value, and cutting away zero and including one for binary number). For example, when the position of the decimal point lies at the eighth bit and the two's complement's 16-bit long signal, if it is positive, then "00000000, 10000000" (=0.5) is added and, if it is negative, then "00000000 01111111" (=0.4961) is added and the numbers lying at the places of the resulting number which are lower than the decimal point are cut away so that they can be rounded. These processes are proposed in a document 1, "Reverse DCT Operation in Motion Picture Processing VISP-LSI" Mochizuki et al, 1990, Telecommunication Association, National Conference Proceedings".
Next, a description is made with reference to the "RND" instruction of the chapter "Assembly Language Instructions" of the document 2 titled "Texas Instrument Third-Generation TMS320 User's Guide 1988, 9".
The instruction format is designated as "RND &lt;src&gt;&lt;dst&gt;". Upon this specification, the result of the rounding operation of the source operand (,src.) is stored into a destination register (&lt;dst&gt;). In this case, the figure is rounded so that it becomes the nearest number of the single precision floating decimal point (that is, the eighth digit below the decimal point of the integer). In the case of the right middle value (that is, x. xxxxxxx5, where x denotes the integer value from 0 up to 9), the rounding operation is carried out in the positive direction.
These processes are specifically described hereinafter.
______________________________________ &lt;src&gt; = 07333C16EEFh = 1.79755599e + 02 &lt;dst&gt; = 0h After the execution of the instruction: &lt;src&gt; = 0733C16EEFh = 1.79755599e + 02 &lt;dst&gt; = 0733C16F00h = 1.79755600e + 02 ______________________________________
As shown above, the rounding operation is achieved by representing the hexadecimal number by the decimal system.
Next, description is made with reference to the "RND" instruction of the chapter "Instruction Set Details" included within a third document "DSP56000 Digital Signal Processor User's Manual 1986".
The instruction format is designated as "RND&lt;dst&gt;". Upon this designation, the result of the rounding operation of the designation register &lt;dst&gt; is stored into the destination register &lt;dst&gt; as it is. The rounding operation of this processor is achieved by adding a constant (hereinafter referred to as a "rounding constant") to the bit to be rounded. In this case, the rounding constant is determined by the value of the scaling bit of the status register. Next, a correspondence between the place of this example where the rounding operation is carried out and the added value is shown in Table 1 below:
TABLE 1 ______________________________________ Round- Status Status ing Register Register Scaling Posi- Rounding Constant 1 2 Mode tion [55 . . . 24, 23, 22 . . . ______________________________________ 0] 0 0 no 23 0 . . . 0 1 10 . . . 0 scal- ing 0 1 scale 24 0 . . . 1 0 00 . . . 0 down 1 0 scale 22 0 . . . 0 0 1 . . . 0 up ______________________________________
According to the RND instruction of the document 2 processor, which is the aforementioned prior art, since a negative number "x, xxxxxxx5" is rounded in the positive direction, it is not possible to round the absolute number by counting fractions over 1/2 as one and cutting away the rest, which in turn makes it impossible to round at the desired bit position. Further, also in the document 3, since the negative number is rounded, it is impossible to round by counting its fractions over 1/2 as one and cutting away the rest leading to the same result.